| शीर्षक | SonicBOOM riscv-boom V2.2.3-210-gd77c2c3f implemented in Chipyard (V1.3.0) Improper Protection of Physical Side Channels |
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| विवरण | RISC-V BOOM (V2.2.3-210-gd77c2c3f) out-of-order CPU cores were discovered to contain a microarchitectural side channel vulnerability. An attacker can exploit write port contention in the L1 data cache to leak secret data by measuring execution time. This vulnerability allows an attacker with local code execution privileges to infer sensitive information handled by other processes or security domains. |
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| स्रोत | ⚠️ https://github.com/fizz-is-on-the-way/vuls_cpu/tree/master/MSHRush |
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| उपयोगकर्ता | lcyf-fizz (UID 82520) |
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| सबमिशन | 30/07/2025 10:35 AM (1 वर्ष पहले) |
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| संयम | 08/08/2025 10:24 PM (9 days later) |
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| स्थिति | स्वीकृत |
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| VulDB प्रविष्टि | 319297 [riscv-boom SonicBOOM तक 2.2.3 L1 Data Cache सूचना का प्रकटीकरण] |
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| अंक | 19 |
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