| 제목 | SonicBOOM riscv-boom V2.2.3-210-gd77c2c3f implemented in Chipyard (V1.3.0) Improper Protection of Physical Side Channels |
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| 설명 | RISC-V BOOM (V2.2.3-210-gd77c2c3f) out-of-order CPU cores were discovered to contain a microarchitectural side channel vulnerability. An attacker can exploit write port contention in the L1 data cache to leak secret data by measuring execution time. This vulnerability allows an attacker with local code execution privileges to infer sensitive information handled by other processes or security domains. |
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| 원천 | ⚠️ https://github.com/fizz-is-on-the-way/vuls_cpu/tree/master/MSHRush |
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| 사용자 | lcyf-fizz (UID 82520) |
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| 제출 | 2025. 07. 30. AM 10:35 (1 년도 ago) |
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| 모더레이션 | 2025. 08. 08. PM 10:24 (9 days later) |
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| 상태 | 수락 |
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| VulDB 항목 | 319297 [riscv-boom SonicBOOM 까지 2.2.3 L1 Data Cache 정보 공개] |
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| 포인트들 | 19 |
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