CVE-2022-50118 in Linux
Summary
by MITRE • 06/18/2025
In the Linux kernel, the following vulnerability has been resolved:
powerpc/perf: Optimize clearing the pending PMI and remove WARN_ON for PMI check in power_pmu_disable
commit 2c9ac51b850d ("powerpc/perf: Fix PMU callbacks to clear pending PMI before resetting an overflown PMC") added a new function "pmi_irq_pending" in hw_irq.h. This function is to check if there is a PMI marked as pending in Paca (PACA_IRQ_PMI).This is used in power_pmu_disable in a WARN_ON. The intention here is to provide a warning if there is PMI pending, but no counter is found overflown.
During some of the perf runs, below warning is hit:
WARNING: CPU: 36 PID: 0 at arch/powerpc/perf/core-book3s.c:1332 power_pmu_disable+0x25c/0x2c0 Modules linked in: -----
NIP [c000000000141c3c] power_pmu_disable+0x25c/0x2c0
LR [c000000000141c8c] power_pmu_disable+0x2ac/0x2c0
Call Trace: [c000000baffcfb90] [c000000000141c8c] power_pmu_disable+0x2ac/0x2c0 (unreliable)
[c000000baffcfc10] [c0000000003e2f8c] perf_pmu_disable+0x4c/0x60
[c000000baffcfc30] [c0000000003e3344] group_sched_out.part.124+0x44/0x100
[c000000baffcfc80] [c0000000003e353c] __perf_event_disable+0x13c/0x240
[c000000baffcfcd0] [c0000000003dd334] event_function+0xc4/0x140
[c000000baffcfd20] [c0000000003d855c] remote_function+0x7c/0xa0
[c000000baffcfd50] [c00000000026c394] flush_smp_call_function_queue+0xd4/0x300
[c000000baffcfde0] [c000000000065b24] smp_ipi_demux_relaxed+0xa4/0x100
[c000000baffcfe20] [c0000000000cb2b0] xive_muxed_ipi_action+0x20/0x40
[c000000baffcfe40] [c000000000207c3c] __handle_irq_event_percpu+0x8c/0x250
[c000000baffcfee0] [c000000000207e2c] handle_irq_event_percpu+0x2c/0xa0
[c000000baffcff10] [c000000000210a04] handle_percpu_irq+0x84/0xc0
[c000000baffcff40] [c000000000205f14] generic_handle_irq+0x54/0x80
[c000000baffcff60] [c000000000015740] __do_irq+0x90/0x1d0
[c000000baffcff90] [c000000000016990] __do_IRQ+0xc0/0x140
[c0000009732f3940] [c000000bafceaca8] 0xc000000bafceaca8
[c0000009732f39d0] [c000000000016b78] do_IRQ+0x168/0x1c0
[c0000009732f3a00] [c0000000000090c8] hardware_interrupt_common_virt+0x218/0x220
This means that there is no PMC overflown among the active events in the PMU, but there is a PMU pending in Paca. The function "any_pmc_overflown" checks the PMCs on active events in cpuhw->n_events. Code snippet:
<<>> if (any_pmc_overflown(cpuhw)) clear_pmi_irq_pending(); else WARN_ON(pmi_irq_pending()); <<>>
Here the PMC overflown is not from active event. Example: When we do perf record, default cycles and instructions will be running on PMC6 and PMC5 respectively. It could happen that overflowed event is currently not active and pending PMI is for the inactive event. Debug logs from trace_printk:
<<>> any_pmc_overflown: idx is 5: pmc value is 0xd9a power_pmu_disable: PMC1: 0x0, PMC2: 0x0, PMC3: 0x0, PMC4: 0x0, PMC5: 0xd9a, PMC6: 0x80002011 <<>>
Here active PMC (from idx) is PMC5 , but overflown PMC is PMC6(0x80002011). When we handle PMI interrupt for such cases, if the PMC overflown is from inactive event, it will be ignored. Reference commit: commit bc09c219b2e6 ("powerpc/perf: Fix finding overflowed PMC in interrupt")
Patch addresses two changes: 1) Fix 1 : Removal of warning ( WARN_ON(pmi_irq_pending()); ) We were printing warning if no PMC is found overflown among active PMU events, but PMI pending in PACA. But this could happen in cases where PMC overflown is not in active PMC. An inactive event could have caused the overflow. Hence the warning is not needed. To know pending PMI is from an inactive event, we need to loop through all PMC's which will cause more SPR reads via mfspr and increase in context switch. Also in existing function: perf_event_interrupt, already we ignore PMI's overflown when it is from an inactive PMC.
2) Fix 2: optimization in clearing pending PMI. Currently we check for any active PMC overflown before clearing PMI pending in Paca. This is causing additional SP ---truncated---
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Analysis
by VulDB Data Team • 12/01/2025
The vulnerability described in CVE-2022-50118 resides within the Linux kernel's performance monitoring unit (PMU) implementation for the powerpc architecture. This issue manifests as a spurious warning condition during the disablement of performance monitoring units, specifically when handling pending performance monitor interrupts (PMI). The root cause stems from a flawed logic in the power_pmu_disable function where a WARN_ON macro is triggered when no active performance monitor counter (PMC) is found to be overflown, yet a PMI is still marked as pending in the Processor Architecture Control Area (PACA). This discrepancy occurs because the system checks for overflow in active events but does not account for the possibility that an inactive event might have caused the overflow, leading to a false positive warning condition.
The technical flaw involves the interaction between multiple kernel components including the hardware interrupt handling mechanism, the performance monitoring unit subsystem, and the PACA structure. The function pmi_irq_pending() introduced in commit 2c9ac51b850d checks for pending PMI in PACA but is used inappropriately within the power_pmu_disable function. The warning is triggered by the condition where any_pmc_overflown(cpuhw) returns false, indicating no active PMC is overflown, yet pmi_irq_pending() returns true, indicating a PMI is pending. This creates a logical inconsistency in the kernel's performance monitoring subsystem, particularly in scenarios involving multiple active and inactive PMCs where overflow events from inactive counters can still generate interrupts.
The operational impact of this vulnerability includes unnecessary system warnings that can clutter kernel logs and potentially mask genuine performance monitoring issues. While the warning itself does not cause system instability or security breaches, it indicates a design flaw in the performance monitoring subsystem that could lead to incorrect assumptions about system behavior. The issue affects systems running the Linux kernel on powerpc architectures where performance monitoring is actively used, particularly in environments where perf tools are employed for profiling and debugging activities. The false positive warnings can complicate system administration tasks and make it more difficult to identify actual performance monitoring problems.
The patch for this vulnerability implements two key optimizations to resolve the issue. First, it removes the WARN_ON(pmi_irq_pending()) statement that was causing the spurious warnings, recognizing that the condition can legitimately occur when an inactive PMC causes overflow while active PMCs do not. This change aligns with the existing behavior in perf_event_interrupt where PMI from inactive PMCs are already ignored, making the warning redundant and potentially misleading. Second, the patch optimizes the clearing of pending PMI by removing the unnecessary check for active PMC overflown before clearing the pending PMI in PACA, thereby reducing unnecessary SPR (Special Purpose Register) reads and improving context switch performance. This optimization addresses the performance overhead introduced by redundant checks and aligns with the principle of minimizing system resource consumption in kernel operations.
From a cybersecurity perspective, this vulnerability aligns with CWE-704 (Incorrect Type Conversion or Cast) and CWE-755 (Improper Handling of Exceptional Conditions) as it involves incorrect handling of exceptional conditions in the performance monitoring subsystem. The vulnerability does not directly impact system security but represents poor software engineering practices in kernel development that could mask more serious underlying issues. The ATT&CK framework categorizes this under T1070 (Indicator Removal on Host) through the generation of misleading system warnings that could obscure legitimate security events. The vulnerability demonstrates the importance of proper exception handling and the need for kernel developers to consider all possible execution paths when implementing performance monitoring features, particularly in complex multi-core architectures where interrupt handling and resource management become critical factors in system stability.