CVE-2026-68330 in Linux
Summary
by MITRE • 08/10/2026
In the Linux kernel, the following vulnerability has been resolved:
net: airoha: Fix DMA direction for NPU mailbox buffer
airoha_npu_send_msg() always maps the mailbox buffer with DMA_TO_DEVICE, but some callers expect the NPU to write response data back into the same buffer:
- airoha_npu_wlan_msg_get() (NPU_OP_GET): NPU writes response into the buffer, then the caller reads it via memcpy() - airoha_npu_ppe_stats_setup() (NPU_OP_SET): NPU writes back npu_stats_addr field in the response
On non-cache-coherent architectures like EN7581 (Cortex-A53 without hardware cache coherency for NPU DMA), DMA_TO_DEVICE unmap is a no-op — it does not invalidate the CPU cache. If the NPU-written cache line is still present in the CPU cache when the caller reads the buffer, the CPU observes stale data instead of the NPU response.
This is a timing-sensitive bug: small mailbox buffers (~24 bytes) typically fit in a single cache line and may survive in the cache until the caller reads them, producing silent data corruption rather than a crash. The bug is more likely to trigger when the caller reads the response immediately after dma_unmap_single() without intervening cache-evicting operations.
Fix by using DMA_BIDIRECTIONAL for both map and unmap, which ensures dma_unmap_single() invalidates the CPU cache on non-coherent systems. The mailbox buffers are small so there is no performance concern.
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Analysis
by VulDB Data Team • 08/10/2026
The vulnerability resides in the Linux kernel's airoha network driver implementation where improper DMA direction handling creates a data corruption scenario affecting memory consistency between the NPU and CPU subsystems. This issue manifests specifically within the airoha_npu_send_msg() function which consistently maps mailbox buffers using DMA_TO_DEVICE flag regardless of whether the NPU needs to write response data back into the same buffer. The problem affects two primary caller functions: airoha_npu_wlan_msg_get() which performs NPU_OP_GET operations where the NPU writes response data directly into the buffer before callers read it via memcpy(), and airoha_npu_ppe_stats_setup() which executes NPU_OP_SET operations where the NPU updates the npu_stats_addr field in the response. The fundamental flaw occurs on cache-coherent architectures like EN7581 based on Cortex-A53 processors without hardware cache coherency for NPU DMA operations, where DMA_TO_DEVICE unmap operations become no-ops that fail to invalidate CPU caches.
The technical implementation defect stems from a misunderstanding of DMA memory access patterns and their interaction with CPU cache management on non-coherent systems. When the kernel maps a buffer with DMA_TO_DEVICE flag, it only ensures data is transferred from CPU memory to device, but does not guarantee cache coherency when data is subsequently written back by the NPU. This creates a scenario where cache lines containing NPU-written data remain resident in the CPU cache, causing callers to observe stale data instead of the actual response. The vulnerability exhibits timing sensitivity because small mailbox buffers typically fitting within single cache lines are more prone to remaining cached until accessed by the calling code, leading to silent data corruption rather than immediate system crashes.
The operational impact of this vulnerability on affected systems is particularly concerning as it produces subtle and hard-to-diagnose data corruption errors that can persist undetected for extended periods. On EN7581 platforms with their specific cache coherency limitations, the bug manifests most frequently when callers immediately read response data after dma_unmap_single() operations without intervening cache management activities that might otherwise evict stale lines. The vulnerability creates a race condition between NPU memory writes and CPU memory reads that becomes more pronounced under specific timing conditions where cache line residency directly impacts data integrity. This type of bug represents a classic cache coherency issue that falls under CWE-367, specifically addressing time-of-check to time-of-use vulnerabilities in memory management contexts.
The mitigation strategy involves changing the DMA mapping direction from DMA_TO_DEVICE to DMA_BIDIRECTIONAL for both mapping and unmapping operations, which ensures proper cache invalidation on non-coherent systems during the dma_unmap_single() operation. This approach maintains full memory consistency while avoiding performance penalties since the mailbox buffers involved are small (approximately 24 bytes) and therefore do not incur significant overhead from bidirectional DMA handling. The fix aligns with ATT&CK framework tactic T1059 by addressing a kernel-level memory corruption vulnerability that could potentially be exploited to manipulate system behavior through data integrity violations, though the current manifestation is more about silent corruption than active exploitation. This resolution effectively addresses the root cause by ensuring proper cache coherency management across all DMA operations involving shared mailbox buffers between CPU and NPU subsystems in the airoha network driver implementation.