CVE-2026-72325 in Linux
Summary
by MITRE • 08/15/2026
In the Linux kernel, the following vulnerability has been resolved:
perf/x86/amd/core: Avoid enabling BRS from the SVM reload path
Branch Sampling (BRS) and Last Branch Record (LBR) are mutually exclusive hardware features, and users of both are tracked via cpuc->lbr_users.
When SVM is toggled on a CPU, the host perf events are reprogrammed to update the HostOnly filter bit (set when virtualization is enabled, cleared when it is disabled). On PerfMonV2-capable processors, this reprogramming is performed by calling amd_pmu_enable_all() to rewrite the event selectors. However, amd_pmu_enable_all() also calls amd_brs_enable_all(), which enables BRS whenever cpuc->lbr_users > 0. Having active LBR events satisfies this gating on processors that have LBR but not BRS. The kernel then tries to set the BRS enable bit in DebugExtnCfg (MSR 0xc000010f). Since that bit is deprecated on such hardware, the write results in a #GP:
Call Trace: <IRQ> amd_pmu_enable_all+0x1d/0x90 amd_pmu_disable_virt+0x62/0xb0 kvm_arch_disable_virtualization_cpu+0xa/0x40 [kvm]
hardware_disable_nolock+0x1a/0x30 [kvm]
__flush_smp_call_function_queue+0x9b/0x410 __sysvec_call_function+0x18/0xc0 sysvec_call_function+0x69/0x90 </IRQ> <TASK> asm_sysvec_call_function+0x16/0x20 RIP: 0010:cpuidle_enter_state+0xc4/0x450 ? cpuidle_enter_state+0xb7/0x450 cpuidle_enter+0x29/0x40 cpuidle_idle_call+0xf5/0x160 do_idle+0x7b/0xe0 cpu_startup_entry+0x26/0x30 start_secondary+0x115/0x140 secondary_startup_64_no_verify+0x194/0x19b </TASK>
Fix this by ensuring that BRS is not enabled from the event selector reprogramming path even when cpuc->lbr_users > 0.
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Analysis
by VulDB Data Team • 08/15/2026
This vulnerability exists in the Linux kernel's performance monitoring unit implementation for x86 processors, specifically affecting AMD systems with SVM (Secure Virtual Machine) capabilities. The issue stems from a race condition and improper state management during virtualization toggling operations. When SVM is enabled or disabled on a CPU, the host perf events undergo reprogramming to update the HostOnly filter bit that distinguishes between virtualized and non-virtualized contexts. This reprogramming process involves calling amd_pmu_enable_all() which serves as a central function for rewriting event selectors on PerfMonV2-capable processors. The flaw occurs because amd_pmu_enable_all() also invokes amd_brs_enable_all(), a function designed to enable Branch Sampling (BRS) functionality.
The technical root cause of this vulnerability lies in the improper handling of mutually exclusive hardware features within the performance monitoring subsystem. Branch Sampling (BRS) and Last Branch Record (LBR) represent two distinct but incompatible hardware capabilities that cannot coexist on the same processor core. The kernel maintains a counter called cpuc->lbr_users to track active users of LBR functionality, which serves as a gating mechanism for enabling BRS features. When virtualization is toggled, the system attempts to enable BRS even when the hardware platform only supports LBR without BRS capability, creating an incompatibility that results in a general protection fault (#GP). This occurs because the kernel tries to write to DebugExtnCfg MSR 0xc000010f to enable the BRS bit, but this bit is deprecated on processors that lack native BRS support, causing the processor to generate an exception.
The operational impact of this vulnerability manifests as a system crash or general protection fault when virtualization is disabled on AMD processors that only support LBR functionality. The call trace reveals a clear execution path through the kernel's performance monitoring subsystem, starting from the SVM reload path and ultimately leading to cpuidle_enter_state where the system attempts to enter idle states. This creates a critical failure point in systems utilizing KVM virtualization with AMD processors, particularly affecting server and cloud environments where dynamic virtualization toggling is common. The vulnerability represents a classic case of improper hardware feature compatibility checking and state management in kernel-level performance monitoring code, potentially leading to denial of service conditions.
The fix implemented addresses this by ensuring that BRS enabling operations are strictly separated from the event selector reprogramming path used during SVM toggling, regardless of the cpuc->lbr_users counter value. This prevents the erroneous enabling of BRS features when the underlying hardware platform does not support them, maintaining proper isolation between mutually exclusive performance monitoring capabilities. The solution aligns with security best practices for virtualization and kernel stability, preventing privilege escalation scenarios that could occur if the system continued to attempt invalid MSR writes. This vulnerability demonstrates the importance of careful hardware feature compatibility checking in low-level kernel subsystems and represents a specific instance where inadequate state management in performance monitoring code led to system instability, particularly relevant to organizations deploying virtualized environments on AMD hardware platforms.
This vulnerability maps to CWE-1210: "Insecure Hardware Feature Configuration" and relates to ATT&CK technique T1059.006: "Command and Scripting Interpreter: Python", though more directly aligns with system-level attack vectors involving kernel exploitation through improper privilege handling. The fix ensures proper isolation between virtualization state management and performance monitoring feature enabling, preventing unauthorized access patterns that could compromise system integrity during virtualization transitions.