CVE-2022-48752 in Linux
요약
\~에 의해 VulDB • 2026. 06. 05.
Based on the kernel log and the description provided, here is an analysis of the issue and the proposed fix.
### Problem Analysis
1. **The Crash/Warning**: * The kernel encountered a warning during `power_pmu_disable`. * The warning states: **"MSR_EE being set (interrupt enabled) when there was an overflown PMC detected."** * This is a consistency check failure. The PowerPC Performance Monitoring Unit (PMU) code expects that when handling a Performance Monitoring Interrupt (PMI) or checking for overflow, interrupts should be in a specific state (usually disabled or carefully managed) to avoid race conditions.
2. **The Context**: * The call trace shows the crash happening during `sys_sched_yield` -> `__schedule` -> `perf_pmu_disable` -> `power_pmu_disable`. * `power_pmu_disable` is called when the PMU is being shut down or reconfigured. * The function runs with **soft interrupts disabled** (`local_irq_save`), but **hard interrupts may still be enabled** (MSR_EE = 1).
3. **The Race Condition**: * Commit `2c9ac51b850d` introduced a fix to clear the pending PMI bit in the `Paca` (Processor Area) structure when disabling the PMU. * However, if a PMC (Performance Monitoring Counter) overflows *while* `power_pmu_disable` is executing, a PMI might be pending or delivered. * If the code clears the pending bit without checking if one is actually pending, or if it clears it while an interrupt is in flight, it can lead to the inconsistent state detected by the warning (MSR_EE set but overflow detected).
### The Fix
The proposed fix is to **check if the PMI pending bit is set in the `Paca` structure before clearing it** via `clear_pmi_pending`.
#### Why this fixes the issue: * **Avoids Unnecessary Clearing**: If no PMI is pending, there's no need to touch the pending bit, avoiding any potential race with an interrupt that might be arriving. * **Ensures Correct State**: If a PMI *is* pending, clearing it explicitly ensures that the PMU state is clean before disabling the PMU. This prevents the scenario where an overflow is detected but the pending flag is not properly handled, leading to the MSR_EE warning. * **Handles the Race**: By checking the pending bit first, the code ensures that it only clears the bit if it was actually set, which is a safer operation in the context of soft-disabled interrupts.
### Code Change (Conceptual)
Instead of directly calling `clear_pmi_pending()`, the code should look something like this:
```c // Before (problematic): clear_pmi_pending();
// After (fixed): if (paca->pmi_pending) {
clear_pmi_pending(); } ```
Or, if `clear_pmi_pending` itself doesn't check, the wrapper or the call site should ensure the check is done.
### Conclusion
The warning is a symptom of a race condition between the PMU disable path and a potential PMI. The fix adds a guard to only clear the pending PMI bit if it is actually set, ensuring that the PMU state is correctly managed even if an overflow occurs during the disable sequence. This prevents the inconsistent state where MSR_EE is set but an overflow is detected.
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