CVE-2022-48752 in Linux
Zusammenfassung
von VulDB • 24.05.2026
Based on the kernel log and the description provided, here is an analysis of the issue and the proposed fix.
### Problem Analysis
1. **The Crash/Warning Context**: * The crash occurs in `power_pmu_disable` during a context switch (`__perf_event_task_sched_out` -> `schedule` -> `sys_sched_yield`). * The specific warning is related to **MSR_EE** (Machine State Register - External Interrupt Enable) being set when an **overflown PMC** (Performance Monitoring Counter) is detected. * On PowerPC, PMU (Performance Monitoring Unit) interrupts are critical for handling counter overflows. If a counter overflows while interrupts are disabled, the hardware may still signal an interrupt pending state, but the software must handle it carefully.
2. **The Root Cause**: * `power_pmu_disable` is called with interrupts **soft-disabled** (`local_irq_save()`), but **not hard-disabled**. This means `MSR_EE` is still set. * The function `commit 2c9ac51b850d` attempted to fix a race condition by clearing the PMI (Performance Monitoring Interrupt) pending bit in the `Paca` (Processor Area) structure before resetting the overflown PMC. * **The Race Condition**: While `power_pmu_disable` is executing, a PMC might overflow. This sets the PMI pending bit in the `Paca`. However, because interrupts are only soft-disabled, the hardware interrupt might still be pending or could be taken if not handled correctly. * The original fix blindly cleared the pending bit. If an overflow occurred *during* the disable sequence, clearing the pending bit without checking if it was already set (or if a new one arrived) could lead to an inconsistent state where the hardware thinks an interrupt is pending, but the software has cleared the flag, potentially causing the kernel to miss the interrupt or crash when it later tries to handle it.
3. **The Fix**: * Before clearing the PMI pending bit via `clear_pmi_pending()`, the code must **check if the PMI pending bit is already set** in the `Paca`. * If it is set, it means an overflow occurred while we were in the process of disabling the PMU. We should not blindly clear it without ensuring the interrupt state is consistent. * The fix ensures that we only clear the pending bit if it was set *before* we started the disable sequence, or handle the case where it was set during the disable sequence appropriately.
### Proposed Code Change
The fix involves modifying the `power_pmu_disable` function in the PowerPC perf code. Here is a conceptual representation of the change:
```c // In arch/powerpc/perf/core-book3s.c (or similar file)
static void power_pmu_disable(struct perf_event *event) {
struct power_pmu *pmu = to_pmu(event->pmu); int idx = event->hw.idx; unsigned long flags;
// ... existing code ...
// Save the current state of the PMI pending bit bool pmi_pending = paca->pmi_pending;
// Disable the PMU for this event // ... code to disable the specific PMC ...
// Check if PMI was pending BEFORE we started disabling if (pmi_pending) {
// Clear the pending bit only if it was set before we started // This avoids clearing a bit that might have been set during // the disable sequence, which could lead to missed interrupts // or inconsistent state. clear_pmi_pending(); }
// ... rest of the function ... } ```
### Explanation of the Fix
1. **Check Before Clear**: The key is to check `paca->pmi_pending` *before* any state changes that might affect it. 2. **Conditional Clear**: Only call `clear_pmi_pending()` if the bit was already set. This ensures that if an overflow occurred *during* the disable sequence, we don't clear the pending bit prematurely, allowing the interrupt handler to process it correctly when interrupts are re-enabled. 3. **Consistency**: This maintains consistency between the hardware interrupt pending state and the software's view of it, preventing the crash caused by MSR_EE being set while an overflown PMC is detected.
### Conclusion
The fix addresses a race condition in the PowerPC PMU disable path by ensuring that the PMI pending bit is only cleared if it was set before the disable sequence began. This prevents inconsistent states that can lead to crashes when interrupts are enabled but an overflow is pending.
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