Submit #625550: SonicBOOM riscv-boom V2.2.3-210-gd77c2c3f implemented in Chipyard (V1.3.0) Improper Protection of Physical Side Channels

RISC-V BOOM (V2.2.3-210-gd77c2c3f) out-of-order CPU cores were discovered to contain a microarchitectural side channel vulnerability. An attacker can exploit write port contention in the L1 data cache to leak secret data by measuring execution time. This vulnerability allows an attacker with local code execution privileges to infer sensitive information handled by other processes or security domains.

• Source: ⚠️ https://github.com/fizz-is-on-the-way/vuls_cpu/tree/master/MSHRush
• User: lcyf-fizz (UID 82520)
• Submission: 07/30/2025 10:35 (1 Year ago)
• Moderation: 08/08/2025 22:24 (9 days later)
• Status: Accepted
• VulDB entry: 319297 [riscv-boom SonicBOOM up to 2.2.3 L1 Data Cache timing discrepancy]
• Points: 19