CVE-2026-50719 in T41
Summary
by MITRE • 08/19/2026
The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing modification of SRAM-resident secure boot state prior to the verification decision. An attacker with physical write access to boot media can inject an init-table entry that disables the secure boot check, causing the ROM to accept unsigned or modified first-stage boot code. This has been hardware-validated on a secureboot-enabled T41 device; ROM analysis confirms closely related behavior on T32, T40, and A1.
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Analysis
by VulDB Data Team • 08/19/2026
The vulnerability identified in the Ingenic T41 System-on-Chip, with high probability extending to the T32, T40, and A1 variants, represents a critical failure in the secure boot chain due to an incorrect ordering of security checks within the hardware Boot ROM. The core technical flaw lies in the execution flow where the processor parses and executes instructions from an attacker-controlled initialization table located in the Secondary Program Loader header before evaluating the secure boot state or invoking signature verification mechanisms. This architectural design choice creates a window of opportunity for malicious actors to manipulate the internal state of the device prior to any cryptographic validation, effectively bypassing the intended security controls through pre-verification state modification rather than breaking the encryption algorithms themselves.
From an operational perspective, this flaw allows an attacker with physical write access to the boot media to inject specific entries into the initialization table that disable or alter the secure boot check logic resident in SRAM. By modifying these critical variables before the verification decision is made, the ROM can be coerced into accepting unsigned or tampered first-stage boot code as legitimate. This capability fundamentally undermines the integrity of the device startup process, enabling the execution of arbitrary code with hardware-level privileges during the earliest stages of system initialization. The vulnerability has been physically validated on a secureboot-enabled T41 device, and static analysis of the ROM firmware confirms that the same logic applies to other chips in the Ingenic family, suggesting a systemic design issue across multiple product lines rather than an isolated incident.
This type of flaw is classified under CWE-284 Improper Access Control, specifically relating to the failure to enforce security policies before executing untrusted input data. Furthermore, it aligns with MITRE ATT&CK techniques related to Bootkit and Early Launch Anti-Malware bypasses, where attackers establish persistence at a level below traditional operating system defenses by compromising the firmware or bootloader stage. The ability to modify SRAM-resident state prior to verification means that even if subsequent stages are signed correctly, the initial trust anchor is compromised because the decision to validate those signatures was made after the attacker had already altered the conditions under which validation occurs.
Mitigation for this vulnerability requires a fundamental redesign of the Boot ROM execution flow to ensure that secure boot checks and signature verifications occur before any user-controlled data or initialization tables are parsed or executed. Hardware manufacturers must implement strict ordering constraints where cryptographic verification is completed first, ensuring that no state modifications can influence the outcome of the security check. For existing devices, software mitigations may be limited due to the nature of the flaw being in immutable ROM code; therefore, reliance on additional hardware-based protections such as secure element isolation or runtime integrity monitoring at later boot stages becomes essential to detect and prevent the execution of compromised early-stage loaders.