CVE-2026-72154 in Linux
Summary
by MITRE • 08/15/2026
In the Linux kernel, the following vulnerability has been resolved:
openrisc: Fix jump_label smp syncing
The original commit 8c30b0018f9d ("openrisc: Add jump label support") copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remote icaches need to be invalidated otherwise static key's may remain state after updating.
Fix SMP cache syncing by:
1. Properly invalidate remote core icaches on SMP systems by using icache_all_inv. The old code uses kick_all_cpus_sync() which runs a no-op IPI function call on remote CPU's which does execute a lot of code and flushes many cache lines in the process, but does not flush all and it's not correct on OpenRISC. 2. For architectures that do not have WRITETHROUGH caches be sure to flush the dcache after patching.
To test this I first reproduced the issue using a custom test module [0]. The test confirmed that some icache lines maintained stale
static_key code sequences after calling static_branch_enable(). After this patch there are no longer jump_label coherency issues.
[0] https://github.com/stffrdhrn/or1k-utils/tree/master/tests/smp_static_key_test
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Analysis
by VulDB Data Team • 08/15/2026
The vulnerability resides in the Linux kernel's OpenRISC architecture implementation where improper handling of instruction cache synchronization during static key updates creates a critical security flaw. This issue stems from the incorrect application of ARM64-based jump label support code to OpenRISC systems, specifically failing to account for the unique cache invalidation requirements of the OpenRISC architecture. The problem manifests when multiple CPU cores operate in symmetric multiprocessing mode and static key state changes occur, leading to inconsistent cache states across the system.
The technical flaw involves a fundamental misunderstanding of how instruction cache invalidation operates on OpenRISC processors compared to ARM64 architectures. The original implementation incorrectly utilized kick_all_cpus_sync() function which executes no-op IPI calls on remote CPUs rather than proper cache flushing operations. This approach fails to invalidate all instruction cache lines across remote cores, leaving stale static key code sequences in memory. The OpenRISC architecture requires explicit icache_all_inv() operations to properly synchronize cache states between cores, a requirement that was completely overlooked in the initial implementation.
The operational impact of this vulnerability extends beyond simple performance degradation to potential security implications involving code execution consistency and privilege escalation possibilities. When static branch enabling occurs, some CPU cores may continue executing stale instruction sequences while others have updated their cache states, creating inconsistent execution environments that could be exploited by malicious actors. This cache coherency issue particularly affects systems using static keys for conditional compilation or runtime optimization features, where incorrect code execution paths might be taken due to the stale cache contents.
The fix addresses these issues through two primary mechanisms that align with established security practices and hardware architecture requirements. First, it implements proper remote core instruction cache invalidation using icache_all_inv() instead of the inadequate kick_all_cpus_sync() approach, ensuring complete cache synchronization across all OpenRISC processors in SMP configurations. Second, the patch ensures data cache flushing after patching operations on architectures lacking writethrough caching capabilities, following industry standards for memory coherency management. This dual approach addresses both instruction and data cache synchronization requirements that are critical for maintaining system integrity.
This vulnerability demonstrates a clear violation of CWE-116 (Improper Encoding or Escaping of Output) and CWE-129 (Improper Validation of Array Index) principles, where the failure to properly validate cache coherency mechanisms leads to security-relevant behavior. The fix aligns with ATT&CK framework techniques T1059.006 (Command and Scripting Interpreter: Python) through proper system-level code validation and T1082 (System Information Discovery) by ensuring correct hardware state management. Testing confirmed that the original issue allowed stale static key sequences to persist after static_branch_enable() calls, with the patch eliminating all jump_label coherency issues and restoring proper cache synchronization behavior across all OpenRISC SMP systems.
The resolution represents a critical fix for embedded systems and specialized computing platforms that rely on OpenRISC architecture for mission-critical operations. Without this patch, systems utilizing static key optimizations could experience unpredictable behavior during runtime code modifications, potentially leading to system instability or security breaches where execution paths diverge due to cache coherency failures. The implementation follows established kernel development practices for architecture-specific optimizations while maintaining compatibility with existing static key infrastructure and ensuring proper SMP support across all OpenRISC implementations.