CVE-2026-78119 in Zephyr
Summary
by MITRE • 10/21/2026
The Nuvoton NPCX eSPI driver parses Target-Attached-Flash (TAF) requests in espi_taf_parse() (drivers/espi/espi_npcx.c), taking the 12-bit length field directly out of the request header in the FLASHRXBUF FIFO. For write and RPMC OP1 requests it copied DIV_ROUND_UP(len, 4) words into struct espi_taf_pckt.src, a fixed 16-word (64-byte) member of a static structure, without ever comparing the length against that buffer or against the negotiated eSPI receive payload size (rx-plsize, 64 bytes on all in-tree NPCX/NPCK SoCs). Both the loop counter and the word count were uint8_t, so the copy ran up to 255 iterations.
An eSPI controller that emits a flash request whose header claims a payload larger than the negotiated maximum therefore drives up to 239 32-bit stores past the end of the structure — roughly 956 bytes of out-of-bounds write into .bss — from the eSPI flash receive interrupt handler, while the source reads walk past the end of the 18-word FLASHRXBUF register array into neighbouring eSPI registers. The same unvalidated length was then passed on to flash_write() in espi_taf_npcx_flash_write() with the 64-byte src buffer as source, reading up to 4 KB of adjacent controller SRAM into SPI flash at a host-chosen address, where the host can read it back. A related fixed-size stack buffer in taf_npcx_completion_handler() was overflowed by four bytes on the maximum-size completion path on SoCs whose tx-plsize is 64.
The defect is reachable only from the eSPI host side, and only by a request that violates the negotiated payload size, so it requires host firmware or bus-level control rather than ordinary host software; a compliant maximum-length write fits the buffer exactly and is handled correctly. Because TAF exists specifically so that the embedded controller arbitrates host access to shared flash (espi_taf_check_read_protect() / espi_taf_check_write_protect()), corrupting controller memory from a host-supplied field crosses the trust boundary the feature asserts; consequences range from controller crash or hang to corruption of driver state that gates the flash protection regions.
The fix widens the counters, rejects any request whose word count exceeds both ARRAY_SIZE(FLASHRXBUF) - NPCX_ESPI_FLASH_HEADER_ADDRESS_LEN and NPCX_TAF_RX_PAYLOAD_WORDS (derived from the devicetree rx-plsize), marks such packets with a new invalid_flag so espi_taf_work() answers them with an unsuccessful completion instead of processing them, bounds the transmit payload against FLASHTXBUF, and adds a default case for unsupported cycle types. Only configurations with CONFIG_ESPI_TAF enabled on an NPCX/NPCK target are affected; no in-tree board enables it by default.
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Analysis
by VulDB Data Team • 10/21/2026
The vulnerability resides within the Nuvoton NPCX embedded controller's eSPI driver, specifically in the espi_taf_parse function which handles Target-Attached-Flash requests. This component is responsible for parsing incoming flash operations from a host system over the enhanced Serial Peripheral Interface bus. The core technical flaw stems from an absence of input validation regarding the payload length field contained within the request header. When processing write and RPMC OP1 commands, the driver extracts a twelve-bit length value directly from the hardware FIFO without verifying it against established constraints. This unchecked integer is then used to calculate the number of words to copy into a fixed-size buffer named src, which has a capacity of sixteen words or sixty-four bytes. The calculation utilizes DIV_ROUND_UP logic but fails to ensure that the resulting word count does not exceed the physical limits of this static structure member.
The operational impact of this flaw is severe due to the nature of memory corruption involved. Because both the loop counter and the calculated word count are defined as eight-bit unsigned integers, they can theoretically support up to two hundred fifty-five iterations regardless of actual buffer capacity. In practice, if a host sends a request claiming a payload larger than the negotiated maximum receive size, which is typically sixty-four bytes on in-tree Nuvoton systems, the driver will perform out-of-bounds writes into adjacent memory regions within the .bss segment. This results in approximately nine hundred fifty-six bytes of unauthorized data being written past the end of the intended buffer structure. Simultaneously, the source read operations traverse beyond the boundaries of the FLASHRXBUF register array, potentially reading sensitive internal controller registers that were not intended to be exposed or manipulated by host-side flash transactions.
Beyond immediate memory corruption, this vulnerability facilitates a more sophisticated attack vector involving data exfiltration and state manipulation. The unvalidated length parameter is subsequently passed to the espi_taf_npcx_flash_write function, which uses the corrupted source buffer as its input. This allows an attacker with control over host firmware or bus-level access to read up to four kilobytes of adjacent controller SRAM content into SPI flash memory at a location chosen by the host. Since the host retains control over this flash region, it can subsequently retrieve and analyze the exfiltrated data, effectively bypassing standard security boundaries. Additionally, on systems with specific transmit payload sizes, a related stack buffer in the completion handler is overflowed by four bytes during maximum-size operations, further destabilizing the controller's execution environment.
From a threat modeling perspective, this defect represents a critical breach of trust between the host and the embedded controller. The Target-Attached-Flash feature is designed to allow the controller to arbitrate access to shared flash memory through read and write protection mechanisms enforced by functions like espi_taf_check_read_protect and espi_taf_check_write_protect. By corrupting driver state via out-of-bounds writes, an attacker can potentially disable these protections or cause a denial of service through system crashes hangs. The vulnerability is classified under CWE-120 Buffer Overflow without Check before Copy and CWE-787 Out-of-bounds Write. In terms of the MITRE ATT&CK framework for embedded systems, this aligns with techniques involving memory corruption to bypass security controls or extract sensitive information from firmware components.
The exploitability of this vulnerability is constrained by specific environmental factors. It requires direct interaction at the eSPI bus level and typically demands host firmware compromise or physical access to manipulate bus signals, as ordinary operating system software cannot directly issue such low-level hardware requests. Furthermore, compliant hosts that adhere to negotiated payload sizes will not trigger the overflow because their writes fit exactly within the buffer limits. However, for systems where CONFIG_ESPI_TAF is enabled on Nuvoton NPCX or NPCK targets, the risk remains significant if connected to untrusted host environments. The lack of default enabling in-tree does not mitigate the inherent danger present when this feature is actively deployed in production deployments.
Remediation efforts focus on rigorous input validation and bounds checking throughout the request processing pipeline. The fix involves widening integer counters from eight-bit to larger types to prevent wrap-around issues during length calculations. Crucially, every incoming request must now be validated against two distinct limits: the available space within the FLASHRXBUF register array minus header overhead, and the negotiated receive payload size derived from device tree configurations. Requests exceeding these thresholds are flagged with an invalid indicator, causing the driver to return a failure completion rather than attempting processing. Additional safeguards include bounding transmit payloads against FLASHTXBUF capacity and implementing default case handlers for unsupported cycle types to prevent undefined behavior in edge cases. These changes ensure that only well-formed requests within expected parameters are processed, thereby preserving memory integrity and maintaining the security boundaries enforced by the flash protection mechanisms.