CVE-2026-72143 in Linux
Summary
by MITRE • 08/15/2026
In the Linux kernel, the following vulnerability has been resolved:
platform/x86: ISST: Restore SST-PP control to all domains
The SST-PP control offset is only restored to power domain 0 after resume. During suspend, control values are read and stored for all power domains.
Use pd_info->sst_base instead of power_domain_info->sst_base, which only points to power domain 0 base address.
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Analysis
by VulDB Data Team • 08/15/2026
This vulnerability resides within the Linux kernel's platform x86 subsystem, specifically affecting the Intel Speed Shift Technology - Power Plane (ISST-PP) implementation. The issue manifests as an incomplete restoration of SST-PP control registers across all power domains during system resume operations. When a system enters suspend state, the kernel correctly reads and stores control values for all power domains, but during the subsequent resume process, it fails to restore these values to their respective domains beyond the first one. This represents a critical flaw in power management functionality that can lead to inconsistent system behavior and potential performance degradation.
The technical root cause stems from improper pointer usage within the kernel's power domain management code. The implementation incorrectly utilizes power_domain_info->sst_base instead of pd_info->sst_base when restoring SST-PP control registers. This pointer misconfiguration results in only the base address for power domain 0 being referenced, effectively ignoring all other power domains that may require their specific SST-PP control settings to be restored. This flaw directly maps to CWE-125: Out-of-bounds Read and CWE-787: Out-of-bounds Write, as the system operates on incorrect memory addresses for non-zero power domains.
The operational impact of this vulnerability extends beyond simple performance issues to potentially compromise system stability and energy efficiency. When SST-PP control registers are not properly restored across all power domains, different CPU cores may operate with inconsistent power management settings, leading to unpredictable thermal behavior, suboptimal power consumption patterns, and potential system instability during high-load operations. This issue particularly affects systems utilizing Intel processors with Speed Shift Technology, where proper power domain coordination is essential for maintaining both performance and energy efficiency targets.
Mitigation strategies should focus on correcting the pointer reference within the kernel's ISST-PP implementation to ensure all power domains receive their appropriate SST-PP control register restoration. System administrators should apply the latest kernel updates that contain the patched implementation, which properly utilizes pd_info->sst_base for all domains rather than the limited power_domain_info->sst_base reference. Additionally, monitoring systems should be implemented to track power domain-specific behavior during suspend/resume cycles, enabling early detection of potential inconsistencies. This vulnerability aligns with ATT&CK technique T1547.004: Boot or Logon Autostart Execution, as improper power management can affect system boot processes and overall runtime stability. Organizations should also consider implementing hardware-specific configurations that enforce proper SST-PP control register handling across all power domains to prevent similar issues in future implementations.