CVE-2026-19571 in Zephyr
Summary
by MITRE • 10/09/2026
The ITE IT8xxx2 SHI host-command backend (subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_ite.c) copied the 8-byte host-command request header from the SPI Rx FIFO directly into the shared receive buffer data->in_msg and only afterwards checked the protocol version and the derived packet length. The interrupt handler also accepted a chip-select assertion and an Rx-valid-length (RVLI) interrupt in any driver state other than SHI_STATE_DISABLED, so a new header could be parsed while the host-command thread was still processing the previous request out of the very same buffer.
The host processor is the SPI controller and drives both chip select and the clock. After sending a well-formed request it can immediately de-assert chip select — which returns the driver to the ready state and re-enables the FIFO — and start a second transaction carrying a header with data_len = 0xFFFF. Those eight bytes are written into in_msg before the oversized length is rejected, so they land in a buffer whose contents verify_rx() in subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c has already validated. If this lands in the window before the host-command thread executes args.input_buf_size = rx_header->data_len, the framework hands the registered command handler a 65535-byte input length over a 256-byte buffer.
The result is an out-of-bounds read of up to roughly 64 KiB beyond the request buffer: command handlers that copy or echo input_buf_size bytes disclose adjacent embedded-controller memory back to the host or overflow the response buffer, and a read past the end of SRAM faults the controller. The same race also allows cmd_id and cmd_ver to be swapped after checksum verification and after handler lookup. Exploitation requires the ability to drive the inter-processor SHI bus (a compromised host OS or physical access to the SPI lines) and winning a timing race, which the SPI controller can retry indefinitely.
The fix parses the header into a local struct ec_host_cmd_request_header and copies it into in_msg only after the length has been bounded by sizeof(data->in_msg), and ignores chip-select and RVLI interrupts outside SHI_STATE_READY_TO_RECV/SHI_STATE_RECEIVING. A residual, bounded race remains: an end-of-transaction interrupt still resets the state to ready while the host-command thread owns the buffer, so a valid second request can still overwrite the in-flight request's contents, unlike the NPCX backend which parks in SHI_STATE_CNL_RESP_NOT_RDY while the buffer is in use.
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Analysis
by VulDB Data Team • 10/09/2026
The vulnerability identified in the ITE IT8xxx2 System Host Interface (SHI) host-command backend represents a critical race condition rooted in improper input validation and state management within the embedded controller firmware. The core technical flaw lies in the sequence of operations performed when processing incoming SPI transactions. Specifically, the driver copies an eight-byte header from the Serial Peripheral Interface receive FIFO directly into the shared receive buffer without first verifying the protocol version or deriving the packet length. This premature data ingestion occurs before any bounds checking is applied to ensure the requested payload size fits within the allocated memory space of 256 bytes. Furthermore, the interrupt handler logic is overly permissive, accepting chip-select assertions and receive-valid-length interrupts in almost all driver states except for a disabled state. This lack of strict state gating allows new headers to be parsed and written into the buffer while the host-command thread is still actively processing a previous request from that same memory region.
The operational impact of this flaw is severe, enabling an attacker with control over the SPI bus or physical access to the inter-processor communication lines to execute arbitrary code disclosure or denial-of-service attacks through precise timing manipulation. By sending a well-formed initial request and immediately de-asserting chip select, an adversary can force the driver back into a ready state that re-enables the FIFO. The attacker then initiates a second transaction with a maliciously crafted header specifying a data length of 65535 bytes. Because the buffer copy happens before validation, these eight bytes are written to the input message structure while the previous request is still being processed by the framework. When the host-command thread eventually executes the code that assigns the input buffer size from this corrupted header, it attempts to read or process up to 64 KiB of data from a buffer that only holds 256 bytes. This results in an out-of-bounds read operation that can disclose adjacent embedded controller memory contents back to the host processor.
Beyond information disclosure, this vulnerability facilitates more destructive outcomes depending on how command handlers utilize the input parameters. If a handler attempts to copy or echo the specified input size, it may overflow the response buffer, leading to stack corruption and potential arbitrary code execution. Alternatively, if the read operation extends beyond the physical SRAM boundaries of the controller, it triggers a hardware fault that can crash the embedded system entirely. The race condition also allows for the manipulation of command identifiers and version numbers after checksum verification but before handler lookup, potentially bypassing security checks or invoking unintended functions. This aligns with CWE-362 (Concurrent Execution using Shared Resource with Improper Synchronization) as it involves a time-of-check to time-of-use scenario where shared resources are accessed without proper synchronization primitives protecting the critical section of buffer management and state transitions.
Mitigation strategies implemented in the fix address these issues by enforcing strict validation before data movement. The corrected code parses the header into a local structure first, ensuring that the packet length is bounded against the size of the receive buffer before any copy operation takes place. Additionally, interrupt handling logic has been tightened to ignore chip-select and RVLI interrupts unless the driver is explicitly in a ready-to-receive or receiving state, preventing concurrent access during processing. However, residual risks remain due to an end-of-transaction interrupt that resets the state to ready while the host-command thread still holds ownership of the buffer. This allows valid second requests to overwrite in-flight request contents, indicating incomplete synchronization compared to other backend implementations like NPCX which maintain a distinct not-ready state during active processing. To fully mitigate this class of vulnerabilities, industry standards such as CWE-367 suggest implementing robust locking mechanisms or atomic operations for shared buffers and ensuring that all state transitions are mutually exclusive with buffer access periods. Security architects should also consider adopting ATT&CK techniques related to privilege escalation via local exploits if the embedded controller manages critical system functions, emphasizing the need for rigorous input validation and strict state machine enforcement in firmware development.