CVE-2026-98946 in Linux
Summary
by MITRE • 10/23/2026
In the Linux kernel, the following vulnerability has been resolved:
drm/vc4: Disable the V3D interrupt across runtime suspend
vc4_irq_disable() masks the V3D interrupt sources and then calls synchronize_irq() before the V3D is powered down. However, by itself, this is not enough to quiesce the interrupt handler.
synchronize_irq() waits for handlers that have already set IRQD_IRQ_INPROGRESS, and for irqchips reporting IRQCHIP_STATE_ACTIVE. A GIC interrupt chip is able to mark an interrupt active as soon as a CPU acknowledges it, so there these checks cover the whole dispatch path. On RPi 0-3, however, the interrupt controller is ARMCTRL, which has no active state. A CPU that has read the hwirq out of the pending register but has not yet reached handle_level_irq() stays invisible to synchronize_irq().
During a power transition, vc4_irq() may therefore run after the power domain is off, where every V3D register read will return 0xdeadbeef. 0xdeadbeef has FLDONE, FRDONE and OUTOMEM set. This problem doesn't trigger NULL pointer dereference issues only because the functions vc4_irq_finish_bin_job() and vc4_irq_finish_render_job() return early when there is no job pointer, but OUTOMEM is still able to schedule vc4_overflow_mem_work() after vc4_irq_disable() has already cancelled it.
Therefore, fix the spurious interrupts by disabling the interrupt line across the PM transition. To preserve the enable/disable balance, move vc4_irq_install() and request the IRQ line disabled before the first runtime resume.
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Analysis
by VulDB Data Team • 10/23/2026
The vulnerability in question resides within the Linux kernel's DRM VC4 driver, specifically concerning the handling of V3D interrupts during power management transitions on Raspberry Pi devices utilizing ARMCTRL interrupt controllers. The core technical flaw stems from an incomplete synchronization mechanism when powering down the V3D hardware block. The original implementation relied on vc4_irq_disable() to mask interrupt sources followed by a call to synchronize_irq(). While this approach is generally sufficient for systems using GIC interrupt chips, it fails on platforms with ARMCTRL controllers because these do not report an active state once acknowledged by the CPU. Consequently, if a CPU has read the hardware IRQ from the pending register but has not yet executed handle_level_irq(), that specific instance remains invisible to synchronize_irq(). This creates a race condition where the power domain can be turned off before all interrupt handlers have fully completed their execution paths.
The operational impact of this flaw is significant due to the behavior of reading registers after the hardware block has been powered down. When the V3D power domain is off, any read operation returns 0xdeadbeef instead of valid register data. This specific value contains flags for FLDONE, FRDONE, and OUTOMEM set high. Although the driver includes safeguards that prevent NULL pointer dereferences in vc4_irq_finish_bin_job() and vc4_irq_finish_render_job() by checking for null job pointers, it fails to account for the spurious OUTOMEM flag generated by the invalid register read. This leads to the scheduling of vc4_overflow_mem_work(), a memory overflow handling routine, even after vc4_irq_disable() has already attempted to cancel pending work items. This results in undefined behavior and potential system instability as the driver attempts to process non-existent or corrupted interrupt events on powered-down hardware.
From a classification perspective, this issue aligns with CWE-362: Concurrent Execution using Shared Resource with Improper Synchronization, specifically involving race conditions during state transitions. It also relates to CWE-459: Incomplete Cleanup, as the driver does not properly quiesce all interrupt handlers before altering power states. In terms of MITRE ATT&CK mapping, this vulnerability can be associated with T1078: Valid Accounts or more broadly with techniques involving privilege escalation through kernel exploitation if an attacker could trigger these race conditions to cause a denial of service or potentially execute arbitrary code via the overflow handling mechanisms, although the primary impact here is stability and reliability rather than direct remote exploitability.
To mitigate this vulnerability, the fix involves disabling the interrupt line across the power management transition rather than relying solely on masking sources and synchronization primitives that are insufficient for ARMCTRL controllers. The solution requires moving vc4_irq_install() to ensure proper initialization sequencing and requesting the IRQ line in a disabled state before the first runtime resume occurs. This ensures that no interrupts can be delivered while the hardware is transitioning between power states, thereby preventing the spurious 0xdeadbeef reads from triggering incorrect interrupt handlers. System administrators should apply kernel updates that include this patch to maintain system stability on affected Raspberry Pi models running older kernels where this race condition remains unpatched.